Amplifier circuit for double sampled architectures

A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.