Technique for reducing a parasitic DC bias voltage on a sensor

Technique for reducing a parasitic DC bias voltage on a sensor

A technique for reducing a parasitic DC bias voltage on a sensor monitors the parasitic DC bias voltage on a first element of the sensor. A controlled bias voltage that is applied between the first element of the sensor and a second element of the sensor is then modified to substantially maintain th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MOWERY KENNETH D, TACKITT DOUGLAS J
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
ELECTRICITY
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES
MEASURING
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A technique for reducing a parasitic DC bias voltage on a sensor monitors the parasitic DC bias voltage on a first element of the sensor. A controlled bias voltage that is applied between the first element of the sensor and a second element of the sensor is then modified to substantially maintain the parasitic DC bias voltage at a desired potential.