Memory array leakage reduction circuit and method

Memory array leakage reduction circuit and method

Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory circuits.

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Bibliographische Detailangaben
Hauptverfasser: CONARY JAMES W, MILLER JEFFREY L, NEMANI MAHADEVAMURTY
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory circuits.