Pll circuit

An arrangement is provided for reducing phase noise of a phase comparator in a PLL circuit. A voltage controlled oscillator (VCO) responsive to a voltage of an input signal controls a frequency of an output signal. An in-loop frequency divider frequency divides the output signal by two to output two output frequency divided signals. An in-loop phase shifter shifts the output frequency divided signals such that they are different in phase by 360 degrees/2 (e.g., 180 degrees). A reference frequency divider frequency divides a reference signal by two to output two reference frequency divided signals. A reference phase shifter shifts the reference frequency divided signals such that they are different in phase by 180 degrees. A plurality of phase comparators output signals in accordance with phase differences between the output frequency divided signals that are different in phase by 180 degrees and respective reference frequency divided signals that are different in phase by 180 degrees, and an adder sums outputs of the plurality of phase comparators. A low-pass filter passes therethrough and applies the low frequency components of the output of the adder to the voltage controlled oscillator.