Manufacture of trench-gate semiconductor devices

A method of manufacturing a trench-gate semiconductor device ( 1 ), the method including forming trenches ( 20 ) in a semiconductor body ( 10 ) in an active transistor cell area of the device, the trenches ( 20 ) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation ( 21 ) in the trenches such that the gate insulation ( 33 ) at the trench bottoms is thicker than the gate insulation ( 21 ) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches ( 20 ), the steps of: (a) forming a silicon oxide layer ( 21 ) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon ( 31 ) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers ( 32 ) on the doped polysilicon ( 21 ) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation ( 33 ) at the trench bottoms; (e) removing the silicon nitride spacers ( 32 ); and (f) depositing gate conductive material ( 34 ) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation ( 33 ) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon ( 31 ) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.