Methods for fast and large circuit simulation

A method for simulating large circuits in full-scale. To enhance the simulation efficiency, subcircuits are extracted from a circuit and thence a hierarchical structure is established using the extracted subcircuits. Subsequently, the circuit is partitioned and a current-voltage table for each subcircuit is dynamically generated. A transient analysis of the circuit is preformed at each incremental time step and a recursive latency check is preformed from the top to the bottom level of the hierarchical structure to determine the active part of the circuit. Using the current-voltage curves, a portion of the conductance matrix corresponding to the active part is rebuild at each incremental time step, which significantly reduces the simulation time.