Test structure for integrated electronic circuits

A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of t...

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Bibliographische Detailangaben
Hauptverfasser:	PARRASSIN THIERRY, DUDIT SYLVAIN, SARDIN PHILIPPE, VALLET MICHEL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS OPTICS PHYSICS SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and the front side of the integrated circuit. This tunnel is designed to channel photons emitted by the switching element towards the front side.