$Programmable fractional N phase locked loop architecture and method$

Programmable fractional N phase locked loop architecture and method

A fractional N phase locked loop (PLL) includes a programmable digital signal processor (DSP) to perform various processing functions within the PLL. In at least one embodiment, the programmable nature of the DSP allows programs to be modified and/or added to the PLL to support a variety of differen...

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Bibliographische Detailangaben
1. Verfasser:	GLASS KEVIN W
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRICITY
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Beschreibung
Zusammenfassung:	A fractional N phase locked loop (PLL) includes a programmable digital signal processor (DSP) to perform various processing functions within the PLL. In at least one embodiment, the programmable nature of the DSP allows programs to be modified and/or added to the PLL to support a variety of different applications.