Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic

An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate cl...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	WEITZEL STEPHEN D, RILEY MACK W, STASIAK DANIEL L, WANG MICHAEL F
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERATION OF NOISE BY SUCH CIRCUITS GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.