Method and device for verifying digital circuits

For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of several pre-defined different implementation alternatives is determined in each case and inserted into the reference description in place of the respective multiplication function, in order subsequently to execute the equivalence test with the reference description changed thereby. In this way, the structural equivalence between the reference description and the digital circuit to be verified can be substantially increased, which speeds up the verification process overall.