System and method to provide a processor with dynamic instruction set and decoder

A system and method to provide a processor with a dynamic instruction set and decoder is provided. One embodiment provides a micro-processor with a dynamic instruction set, the instruction set is updated on the fly. A single instruction can be interpreted in many different ways depending on the current configuration of the instruction decoder. This configuration is not restricted to a single or a few modes, but can take many different values. The configuration can be adapted by explicit instructions in the instruction stream or as a side effect of other instructions being executed. The advantage of updating the instruction set is in the coding efficiency. E.g., the total number of instructions that can be executed by the functional units may exceed the instruction set size, which can be limited by the maximum instruction (bit string) length. By adapting the instruction set dynamically, the instructions that are important for certain functions can be made available when those functions are executed but be swapped out while other functions are executed. In that way, the instruction set is at any time optimal for the task at hand.