Memory array with staged output

Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the...

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Bibliographische Detailangaben
Hauptverfasser: YUKER CHRIS E, JOURDAN STEPHAN J, PHELPS BOYD S
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.