Semiconductor integrated circuit

To provide a semiconductor integrated circuit in which a clock signal supplied to each flip-flop will not be adversely affected when a functional change is made using a spare flip-flop. The semiconductor integrated circuit includes a plurality of main flip-flops which contribute to a predetermined function, a plurality of spare flip-flops, and a clock tree synthesis circuit that generates a clock signal which is adjusted for synchronizing the plurality of main flip-flops and the plurality of spare flip-flops and supplies the adjusted clock signal to the plurality of main flip-flops and the plurality of spare flip-flops.