Varying cue delay circuit

An integrated circuit for an ink jet printer includes a state machine with numerous sequenced logic circuits to generate buffered control signals from the tachometer input. A counter counts one of the buffered control signals from the state machine forming a write address. A synchronous up-down counter receives a cue delay value when the up-down counter receives a buffered control signal thereby forming a delayed count. An adder receives the write address and the delayed count and generates a read address. A comparator compares the delayed count to the cue delay value and sets a comparator output depending upon whether the delayed count is greater than or less than the cue delay value. A multiplexer receives the read and write addresses and the buffered control signals and sends a single to RAM. A logic circuit receives the buffered control signals and outputs a delayed cue signal to the printing system.