Test structures and method for interconnect impedance property extraction

A method and test structures are disclosed for characterizing interconnects of an integrated circuit. The method provides a set of test structures and determines a unit impedance property of each test structure, desirably using S-parameter measurements. A reference impedance data set is then formulated that characterizes the impedance of an integrated circuit manufacturing technology and that can be used to characterize the impedance of interconnects of the chip made by the technology. Each test structure desirably comprises a ground grid and a signal line, and is characterized by values of a set of predetermined attributes such as layer location of the respective ground grid, grid density, layer association, width and length of the respective signal line.