Transistor fabrication methods using reduced width sidewall spacers

Transistor fabrication methods using reduced width sidewall spacers

Transistor fabrication methods ( 50 ) are presented in which shrinkable sidewall spacers ( 120 ) are formed ( 66, 68 ) along sides of a transistor gate ( 114 ), and a source/drain implant is performed ( 74 ) after forming the sidewall spacer ( 120 ). The sidewall spacer width is then reduced by anne...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHIDAMBARAM PR, BU HAOWEN, KHAMANKAR RAJESH
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Transistor fabrication methods ( 50 ) are presented in which shrinkable sidewall spacers ( 120 ) are formed ( 66, 68 ) along sides of a transistor gate ( 114 ), and a source/drain implant is performed ( 74 ) after forming the sidewall spacer ( 120 ). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material ( 76 ) following the source/drain implant ( 74 ).