Receiver and method for mitigating temporary logic transitions

A circuit and method for receiving data signals over a data signal line are disclosed. In one embodiment, a receiver circuit is provided for receiving data signals transmitted over a signal line. The receiver circuit comprises an inverter circuit having an input that forms an input of the receiver circuit and an output coupled to an internal node, an output circuit having an input coupled to the internal node and an output that provides an output of the receiver circuit, and a charge adding circuit that provides at least a portion of a temporary logic transition at the input of the receiver circuit, induced by a logic transition on an adjacent signal line, to the internal node to mitigate erroneous logic transitions associated with the receiver circuit.