Digital multifunctional imaging apparatus

In a digital multifunctional apparatus, an image processing circuit which is configured by a hardware circuit compares a value of each image data of pixel with a predetermined threshold value so as to binarize the value of such image data, and calculates an error component, and further adds a product obtained by multiplying the error component and predetermined coefficient to an initial values of the image data of each pixel. By sequentially performing such binarization and addition with respect to each pixel, it is possible that while reading the image data of a document, the image processing circuit quickly performs the quasi-halftone processing to the image data without increasing burden of a CPU. Thus, the quasi-halftone processing can be achieved using an inexpensive CPU without using a DSP and expensive CPUs having high operating clock frequencies, thereby reducing cost of the digital multifunctional apparatus.