Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). The method comprises growing an oxide layer ( 120 ) on a gate structure ( 114 ) and a substrate ( 102 ) and implanting a dopant ( 124 ) into the substrate ( 102 ) and the oxide layer ( 120 ). Implantation is such that a portion of the dopant ( 124 ) remains in the oxide layer ( 120 ) to form an implanted oxide layer ( 126 ). The method further includes depositing a protective oxide layer ( 132 ) on the implanted oxide layer ( 126 ) and forming etch-resistant off-set spacers ( 134 ). The etch-resistant off-set spacers ( 134 ) are formed adjacent sidewalls of the gate structure ( 114 ) and on the protective oxide layer ( 132 ). The etch resistant off-set spacers having an inner perimeter ( 135 ) adjacent the sidewalls and an opposing outer perimeter ( 136 ). The method also comprises removing portions of the protective oxide layer ( 132 ) lying outside the outer perimeter ( 136 ) of the etch-resistant off-set spacers ( 134 ). Other embodiments of the present invention include a transistor device ( 200 ) and method of manufacturing an integrated circuit ( 300 ).