Method and apparatus for functional language temporal extensions, dynamic modeling, and verification in a system-level simulation environment

A method and apparatus for functional simulation of a system 104 in a system-level simulation and verification environment using a functional language 100 derived from a selected Scheme Language standard, and a simulator 105 for simulating verification functions 101 and model functions 102 expressed in the functional language 100 . The functional language 100 has syntax extensions expressed as dynamic "always @" and "@" blocks, and all other event expressions which are similar to Verilog and other RTL (Register-Transfer Level) HDL (Hardware Description Language) temporal syntax constructs. A composer 103 is further used to connect verification functions 101 with model functions 102 . Model functions 102 , represented as mutable state functional objects along with selected test, monitor, checker and user-defined functions, sample reactive responses and ensure concurrent drive of abstracted signals for the simulator 105 . The simulator 105 can function as a formal verifier to formally verify the model functions 102 , or a synthesizer to transform programs written in a restricted subset of the functional language 100 into an internal control and data flow format or any synthesis-ready language. A system-level modeling and simulation environment enhanced with a graphical user interface facilitates the usage of the functional language 100.