Method and system for delay defect location when testing digital semiconductor devices

Method and system for delay defect location when testing digital semiconductor devices

An invention is disclosed which automates the discovery in a digital logic semiconductor device of the location of a defect which causes signals to propagate in a manner delayed from the defect free condition. A tester operating system controls application of test patterns designed for delay fault d...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DOEGE JASON, ORGAN DONALD V
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An invention is disclosed which automates the discovery in a digital logic semiconductor device of the location of a defect which causes signals to propagate in a manner delayed from the defect free condition. A tester operating system controls application of test patterns designed for delay fault discovery and causes a static timing verifier application to choose additional paths to test which in combination, elucidate the location to one segment of the problematical path.