FEATURE TARGETED INSPECTION

A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk fe...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	MADGE ROBERT
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR CALCULATING CINEMATOGRAPHY COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.