Shift register for safely providing a configuration bit

Shift register for safely providing a configuration bit The invention relates to a shift register cell ( 1 -i , 100 -i) for safely providing a configuration bit ( 6 -i) having a master latch ( 8 -i) which can be connected to a serial data input ( 2 -i) on the shift register cell ( 1 -i , 100 -i) for the purpose of buffer-storing a data bit ( 3 -i); a first slave latch ( 10 -i) which can be connected to the master latch ( 8 -i) for the purpose of buffer-storing the data bit; at least one second slave latch ( 12 -i) which can be connected to the master latch ( 8 -i) for the purpose of buffer-storing the data bit, and having an evaluation logic unit ( 13 -i) which outputs the configuration bit ( 6 -i) on the basis of the data bits which are buffer-stored in the master latch ( 8 -i) and in the slave latches ( 10 -i , 12 -i). In addition, the invention provides a shift register ( 17 ) for safely providing configuration bits ( 6 - 1, . . . 6 -N) which has a plurality of inventive shift register cells ( 1 - 1, . . . 1 -N, 100 - 1, . . . 100 -N) which are connected in series to form a shift register chain ( 1, 100 ).