Repatterned integrated circuit chip package
A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.
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| Hauptverfasser: | , |
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| Format: | Patent |
| Sprache: | eng |
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| Online-Zugang: | Volltext bestellen |
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| Zusammenfassung: | A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency. |
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