Nonvolatile semiconductor memory device

The present invention employs a memory cell structure in that one end of a variable resistance element ( 1 ) for storing information by change of electric resistance is connected to a source of a selection transistor ( 2 ) to form a memory cell ( 3 ) and, in a memory cell array ( 4 ), a drain of the selection transistor ( 2 ) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element ( 1 ) is connected to a source line (SL) and a gate of the selection transistor ( 2 ) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell ( 3 ) is carried out for each of sectors including the plural memory cells ( 3 ) commonly connected to the source line (SL).