System and method for stress free conductor removal

A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive interconnect material filling multiple features in the pattern. The first conductive interconnect material having an overburden portion. The over burden portion is planarized. The over burden portion is substantially entirely removed in the planarizing process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized over burden portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.