VARIABLE DELAY ELEMENT FOR USE IN DELAY TUNING OF INTEGRATED CIRCUITS

A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KUPPUSWAMY RAVISHANKAR, TAYLOR GREGORY
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes a variable delay upon the input signal for testing and evaluation.