Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels

Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels

A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BECK DOUGLAS JAMES, RAINALDI WILLIAM MICHAEL
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BECK DOUGLAS JAMES
RAINALDI WILLIAM MICHAEL
description A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004225924A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004225924A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004225924A13</originalsourceid><addsrcrecordid>eNqNjLEKAjEQRK-xEPUfFqyFM56FpYhiY6XWx5Lb3AVym5DdE_TrTeEHWAzDPIY3r9yNdIgdIJekhBl1EnAxw1im5x7E94xBIDpA6OjlLcHEHWVQEgWNEGLvbTFgeH8KHgllyjQSK9gBmSnIspq5IqHVrxfV-nJ-nK4bSrElSWiJSdvn3dR1Y8z-YJrjdvff6wtQcUBz</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels</title><source>esp@cenet</source><creator>BECK DOUGLAS JAMES ; RAINALDI WILLIAM MICHAEL</creator><creatorcontrib>BECK DOUGLAS JAMES ; RAINALDI WILLIAM MICHAEL</creatorcontrib><description>A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration.</description><edition>7</edition><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041111&amp;DB=EPODOC&amp;CC=US&amp;NR=2004225924A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041111&amp;DB=EPODOC&amp;CC=US&amp;NR=2004225924A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BECK DOUGLAS JAMES</creatorcontrib><creatorcontrib>RAINALDI WILLIAM MICHAEL</creatorcontrib><title>Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels</title><description>A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKAjEQRK-xEPUfFqyFM56FpYhiY6XWx5Lb3AVym5DdE_TrTeEHWAzDPIY3r9yNdIgdIJekhBl1EnAxw1im5x7E94xBIDpA6OjlLcHEHWVQEgWNEGLvbTFgeH8KHgllyjQSK9gBmSnIspq5IqHVrxfV-nJ-nK4bSrElSWiJSdvn3dR1Y8z-YJrjdvff6wtQcUBz</recordid><startdate>20041111</startdate><enddate>20041111</enddate><creator>BECK DOUGLAS JAMES</creator><creator>RAINALDI WILLIAM MICHAEL</creator><scope>EVB</scope></search><sort><creationdate>20041111</creationdate><title>Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels</title><author>BECK DOUGLAS JAMES ; RAINALDI WILLIAM MICHAEL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004225924A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>BECK DOUGLAS JAMES</creatorcontrib><creatorcontrib>RAINALDI WILLIAM MICHAEL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BECK DOUGLAS JAMES</au><au>RAINALDI WILLIAM MICHAEL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels</title><date>2004-11-11</date><risdate>2004</risdate><abstract>A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2004225924A1
source esp@cenet
subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T07%3A34%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BECK%20DOUGLAS%20JAMES&rft.date=2004-11-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2004225924A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true