Method and apparatus for mapping signals of a device under test to logic analyzer measurement channels
A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may t...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A method of mapping device pins to logic analyzer channels in preparation for a digital test includes accepting a correlation of at least one test connector to one or more logic analyzer pods and presenting a display showing available test connector pins for each defined test connector. A user may then select a one to one assignment of one or more signal pins to the test connector pins to establish a mapping configuration. |
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