Embeddable method and apparatus for functional pattern testing of repeatable program instruction-driven logic circuits via signal signature generation

An embeddable method and apparatus for functional pattern testing of repeatable program instruction-driven logic circuits via signal signature generation provides an improved mechanism for functional testing of integrated circuits. The apparatus may be embedded within a processor having an exerciser program loaded within an internal cache and includes one or more multiple input shift registers (MISR) coupled to a set of selected internal signal points within functional blocks of the integrated circuit for collecting a signature in response to state changes of the internal signal points caused by execution of the exerciser program. The signature is compared to a known good signature to generate pass/fail or diagnostic information during design/mask evaluation, manufacturing testing, and/or as a screening test during diagnostic boot in a production environment. A logic analyzer may also be implemented using the MISR, providing an efficient mechanism for verifying a lengthy response of logic circuits without requiring a large trace buffer. The exerciser program may be located within a device under test (DUT), external to the DUT, or may be located within the logic analyzer and provided with stimulus outputs for driving state changes of the measured signals in the DUT from the analyzer. The exerciser program may be self-modifying or self-test-case-generating, reducing the code size required to exercise a large pattern through the DUT.