Semiconductor memory device

A semiconductor memory device for realizing high speed writing while maintaining credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.