Operand forwarding in a superscalar processor

A method and mechanism for improving Instruction Level Parallelism (ILP) of a program and eventually improving Instructions per cycle (IPC) allows dependent instructions to be grouped and dispatched simultaneously by forwarding the oldest instruction, or source instruction, General Register (GR) data to the other dependent instructions. A source instruction of a load type loading a GR value into a GR. The dependent instructions will then select the forwarded data to perform their computation. The dependent instructions use the same GR read address as the source instruction. Another source instruction of a load type loads a memory data into a GR. The loaded memory data is forwarded or replicated on the memory read bus of the other dependent instructions. The mechanism allows Address Generator Output to be forwarded to the other dependent instructions when the source instruction is a load type loading a memory address into a GR. Then the loaded address is forwarded or replicated on the address bus of the other dependent instructions. Then, also, Control Register (CR) data is forwarded to the other dependent instructions when the source instruction is a load type loading a CR value into a General Register. Then the loaded CR data is forwarded or replicated on the CR data bus of other dependent instructions. When the source instruction is a load type loading an immediate value into a General Register, loaded immediate data is forwarded or replicated on the immediate data bus of other dependent instructions.