Surge counter/detector apparatus, system and method

A surge counter/detector apparatus includes current sensors communicating with power lines to sense a surge condition. A trigger circuit communicates with the current sensors and outputs a first signal in response to the sensed surge condition. The trigger circuit is reset and enabled by a second signal in order to enable subsequent output of the first signal. A processor detects the first signal from the trigger circuit and responsively increments and displays a count value at a display. The processor provides the second signal having a first state to reset the trigger circuit and a second state to enable the trigger circuit. The processor includes a timer to vary a time between (a) detecting the first signal, and (b) resetting and enabling the trigger circuit.