Testing logic and embedded memory in parallel

Testing logic and embedded memory in parallel

Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KESSLER BRIAN R, OBREMSKI THOMAS E, WHEATER DONALD L, CORBIN WILLIAM R, NELSON ERIK A
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Beschreibung
Zusammenfassung:Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.