METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR

METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR

A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.

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Bibliographische Detailangaben
Hauptverfasser: AZAM MISBAHUL, PEARSE JEFFREY, HANNOUN DANIEL G
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.