Topography correction for testing of redundant array elements

A data topography correction circuit for a semiconductor memory device and method for testing the device is provided. The data topography correction circuit includes a redundant hit circuit for determining if a redundant element has been used to replace a defective element; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective element to a data topology of the redundant element. The method includes the steps of providing an address of a memory array element of the device to be tested; determining if the memory array element has been replaced with a redundant element; and, if the memory array element has been replaced, correcting test data to the data topology of the redundant element.