Processor system with cache-based software breakpoints

Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory. In an illustrative embodiment, each of the processors in a shared-memory multiprocessor system has an instruction cache associated therewith. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address. After a determination has been made, from the control indicator having been set to the first state, that the breakpoint code will be returned to the given processor from the instruction cache in response to the first fetch request, the control indicator associated with the particular location is set to a second state which directs that a second fetch request to the corresponding address be serviced from the main memory. The control indicator state is then changed again, e.g., reset back to the first state, after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address will be serviced from the main memory. While the control indicator is set to the first state, a miss event in the instruction cache does not lead to replacement of the breakpoint code in the particular location in the instruction cache.