Digital to digital sigma-delta modulator and digital frequency synthesizer incorporating the same

A digital to digital Sigma-Delta modulator comprises an input which receives a digital input value encoded over N bits, an output which delivers a digital output value encoded over n bits, where n is less than N, and at least a first Sigma-Delta cell which includes a quantizer having a quantization interval which is a prime number. The choice of a prime number decreases the power of the limit cycles (lines with a power value higher than the local mean value) which may appear depending on the input code of the modulator and on the initial conditions. Application is proposed to a digital frequency synthesizer.