Method and apparatus for multi-core on-chip semaphore

Method and apparatus for multi-core on-chip semaphore

A method and apparatus for implementing a semaphore on a multi-core processor including a central arbitration unit (CAU) connected to each core thereof. The scheme involves, for each core, outputting a first signal from the core to the CAU to request access to a common resource to perform an operati...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: SEDMAK MICHAEL C
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A method and apparatus for implementing a semaphore on a multi-core processor including a central arbitration unit (CAU) connected to each core thereof. The scheme involves, for each core, outputting a first signal from the core to the CAU to request access to a common resource to perform an operation; and responsive to receipt of a second signal from the CAU, the core performing the operation.