Pad connection structure of embedded memory devices and related memory testing method

In a pad connection structure for a plurality of embedded memory devices in a system-on-a-chip configuration, common pads are separately allotted to signal lines of embedded memory devices used for identical purposes and corresponding multiplexers are connected between the common pads and the signal lines of the embedded memory devices, thereby significantly reducing the number of input and output pads of the memory merged logic, minimizing damage to the pads, as a result of low probing frequency, and sequentially testing the embedded memory devices in a single testing operation.