High speed parallel link receiver

A digital system is provided with a means for achieving alignment between a set of serial data receiver demultiplex circuits, thereby achieving alignment of the bits in the data words, while maintaining the use of separate and therefore optimally aligned data recovery clocks for each channel signal. The digital system is provided with circuitry for generating a reference clock signal and clock circuitry for generating one or more slave clock signals. Phase circuitry is connected to receive the slave clock signal and has outputs for providing a plurality of clock phase signals. A phase selection circuit is connected to receive the plurality of clock phase signals. The phase selection circuit has an output for providing an adjusted clock signal selected from the plurality of clock phase signals in response to a phase selection signal. A clock correlation circuit is connected to receive the reference clock signal and the adjusted clock signal and the clock correlation circuit is operable to determine a phase difference between the reference clock signal and the adjusted clock signal and to provide the phase selection signal such that the phase difference is minimized. The clock correlation circuit comprises a counter and the phase selection signal is a count value output by the counter. The clock correlation circuit further comprises a plurality of digital to analog converters each with an output connected to a respective input of a first comparator for asserting a decrement signal or a second comparator for asserting an increment signal, wherein each digital to analog converter comprises an exclusive-or gate having an output connected to an integrator, such that an output of the integrator is the output of the digital to analog converter.