Soft error recovery in microprocessor cache memories

A method and apparatus for protecting cache memories from soft errors. Entries in the cache's data store and tag memory are associated with parity bits. During a read cycle, the parity bits are checked and data retrieved only if the parity checks indicate no errors.

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Bibliographische Detailangaben
Hauptverfasser:	TAYLOR RICHARD D, ALLEN GREG L
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A method and apparatus for protecting cache memories from soft errors. Entries in the cache's data store and tag memory are associated with parity bits. During a read cycle, the parity bits are checked and data retrieved only if the parity checks indicate no errors.