Method and circuit to implement double data rate testing
A DDR apparatus is provided that includes a pattern generating device to generate a clock test pattern and a data test pattern and buffer devices to receive the clock test pattern and the data test pattern. A pattern checking device checks patterns received from the buffer devices. Clock generating...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A DDR apparatus is provided that includes a pattern generating device to generate a clock test pattern and a data test pattern and buffer devices to receive the clock test pattern and the data test pattern. A pattern checking device checks patterns received from the buffer devices. Clock generating logic controls a clock for the clock test pattern and a clock for the data test pattern. |
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