Differential amplifier circuit

The first amplifier circuit D1 is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM1 respectively to the drains of P-channel MOS transistors 1 and 2 as a differential input portion, and the second amplifier circuit D2 is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM2 respectively to the drains of N-channel MOS transistors 5 and 6 as a differential amplifier circuit. The first and second differential amplifier circuits D1 and D2 can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.