SDRAM interface control system and method

Systems and methods of controlling the timing of a clock signal used to latch information from one or more memory modules, such as SDRAM modules. The invention relates to generating a latch or read clock signal that relates to the actual SDRAM control clock signal. The generated clock signal accounts for variances due to PVT and PCB trace lengths. In one embodiment, the generated clock signal is fed back from the SDRAM module. That is, the SDRAM control clock signal is conducted serially to the one or more SDRAM modules and then back to the controller. As such, the read clock signal is essentially the same as the SDRAM clock signal. However, the read clock signal is delayed before its return to the controller due to PVT and trace length issues. Importantly however, these delays are similar to the delays associated with the read line information, such that the controller has a significantly precise understanding of when the information on the read lines is available for latching into its buffers.