Automatic generation of interconnect logic components
A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be "off-chip'. The architecture includes a data aggregat...
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Zusammenfassung: | A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be "off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration. |
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