Automatic layout design method of wirings in semiconductor integrated circuit

The present invention provides a method for completing detailed wiring of a semiconductor integrated circuit as intended by the layout designer in a short period of time. The method comprises the steps of: determining a floor plan of a semiconductor integrated circuit chip; displaying the floor plan...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MOGAKI MASATO, MUNEMURA TAIZO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!