Automatic layout design method of wirings in semiconductor integrated circuit

The present invention provides a method for completing detailed wiring of a semiconductor integrated circuit as intended by the layout designer in a short period of time. The method comprises the steps of: determining a floor plan of a semiconductor integrated circuit chip; displaying the floor plan with lattice lines superimposed thereon; if unit coordinate areas (lattice fields) included in a target interblock net and the order in which they are traced are specified, setting the coordinate values of the lattice fields and the order as a rough wiring path, the unit coordinate areas being defined by neighboring lattice lines; determining detailed layouts of gates; and performing automatic detailed wiring on condition that the target interblock net goes through the set rough wiring path (exists within the set rough wiring path).