Increasing the electrical activation of ion-implanted dopants

We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device includes the steps of providing a single cryst...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PELAZ-MONTES MARIA LOURDES, RAFFERTY CONOR STEFAN, VENEZIA VINCENT C, GOSSMANN HANS-JOACHIM LUDWIG, KALYANARAMAN RAMKI, HAYNES TONY E
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device includes the steps of providing a single crystal semiconductor body, implanting vacancy-generating ions into a preselected region of the body, implanting dopant ions into the preselected region, the dopant implant forming interstitial defects in the body, and annealing the body to electrically activate the dopant ions. Importantly, in our method the vacancy-generating implant introduces vacancy defects into the preselected region that are effective to annihilate the interstitial defects. In addition, process steps that amorphize the surface of the implanted region are avoided, and the dose of the vacancy-generating implant is made to be greater than that of the dopant implant. In a preferred embodiment, the peak of the vacancy defect concentration profile substantially overlaps the peak of the dopant implant concentration profile. In another preferred embodiment the peak of the vacancy-generating implant profile is deeper than that of the dopant profile. In accordance with another aspect of our invention, after ion implantation is complete, only low temperature process steps (e.g., steps performed at temperatures no greater than about 800° C. for Si devices) are performed.