PROGRAMMABLE BURST FIFO

PROGRAMMABLE BURST FIFO

A programmable burst FIFO buffer (100) allows for burst of data to be loaded into memory (106) without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer (100) is also programmable and allows for "N" words to be loade...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: HEARN ALAN S
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:A programmable burst FIFO buffer (100) allows for burst of data to be loaded into memory (106) without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer (100) is also programmable and allows for "N" words to be loaded with "N" being programmable in any given burst without having to check for a buffer full condition. The buffer (100) also avoids the glitches associated with other buffer designs due to the write and read clock being in different domains.